URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 168

Rev	Log message	Author	Age	Path
168	modify program list.	simont	7690d 19h	/
167	add readmem for ea.	simont	7694d 00h	/
166	Change test monitor from ports to external data memory.	simont	7694d 17h	/
165	remove dumpvars.	simont	7694d 22h	/
164	initial inport.	simont	7694d 22h	/
163	initial inport	simont	7694d 22h	/
162	initial inport.	simont	7694d 23h	/
161	fix file names.	simont	7694d 23h	/
160	initial inport.	simont	7694d 23h	/
159	initial inport.	simont	7694d 23h	/
158	fix bug.	simont	7694d 23h	/
157	change data output.	simont	7694d 23h	/
156	add FREQ paremeter.	simont	7694d 23h	/
155	add aditional tests.	simont	7694d 23h	/
154	File name fixed.	simont	7695d 18h	/
153	`ifdef added.	simont	7696d 17h	/
152	sub_result output added.	simont	7696d 17h	/
151	remove pc_r register.	simont	7696d 17h	/
150	fix some bugs.	simont	7696d 17h	/
149	pipelined acces to axternal instruction interface added.	simont	7696d 17h	/
148	include "8051_defines" added.	simont	7696d 18h	/
147	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7718d 18h	/
146	fix bug in movc intruction.	simont	7718d 18h	/
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7723d 22h	/
144	chsnge comp.des to des1	simont	7723d 22h	/
143	add wire sub_result, conect it to des_acc and des1.	simont	7723d 22h	/
142	optimize state machine.	simont	7724d 23h	/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7725d 01h	/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7725d 01h	/
139	add aditional alu destination to solve critical path.	simont	7725d 19h	/