URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 40

Rev	Log message	Author	Age	Path
40	added sigals for interacting with external ram	simont	7974d 17h	/
39	added signals ack, stb and cyc	simont	7981d 15h	/
38	fix some bugs	simont	7981d 15h	/
37	added signals ack, stb and cyc	simont	7981d 16h	/
36	fix bugs in mode 0	simont	7981d 16h	/
35	design docunemt	simont	7982d 14h	/
34	specification docunemt	simont	7982d 14h	/
33	fix some bugs	simont	7982d 20h	/
32	overflow repaired	simont	7982d 20h	/
31	fix some bugs	simont	7989d 12h	/
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	7992d 19h	/
29	fix some bugs	simont	7992d 19h	/
28	remove syn signal	simont	7992d 20h	/
27	fix some bugs	simont	7992d 20h	/
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	7992d 22h	/
25	divider and multiplier pass test	markom	7993d 16h	/
24	intensively tests all instructions	markom	7993d 21h	/
23	mul & div use 4 clocks	simont	7994d 11h	/
22	fix some bugs	simont	7994d 11h	/
21	mul bug fixed	markom	7994d 17h	/
20	multiplier and divider changed so they complete in 4 cycles	markom	7994d 19h	/
19	combinatorial loop removed	simont	7995d 12h	/
18	rst signal added	simont	7998d 17h	/
17	fix some bugs	simont	7998d 17h	/
16	inputs ram and op2 removed	simont	7998d 17h	/
15	commbinatorial loop removed	simont	7998d 17h	/
14	added signal ea_int	simont	7998d 18h	/
13	some bug fix	simont	7999d 15h	/
12	des1_r in alu port list	simont	7999d 15h	/
11	des2_r removed	simont	7999d 15h	/