URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 55

Rev	Log message	Author	Age	Path
55	added parameter DELAY	simont	7928d 11h	/
54	cahnge interface to instruction rom	simont	7928d 11h	/
53	initial CVS inport	simont	7928d 11h	/
52	fix bugs	simont	7928d 11h	/
51	fix bugs	simont	7930d 16h	/
50	fix bugs	simont	7930d 17h	/
49	verification added	simont	7937d 16h	/
48	added program for rom converting	simont	7945d 12h	/
47	remove unused files	simont	7945d 12h	/
46	prepared header	simont	7945d 12h	/
45	prepared header	simont	7945d 13h	/
44	prepared header	simont	7945d 13h	/
43	remove unused files	simont	7945d 14h	/
42	* empty log message *	simont	7945d 14h	/
41	remove unused files	simont	7945d 15h	/
40	added sigals for interacting with external ram	simont	7965d 16h	/
39	added signals ack, stb and cyc	simont	7972d 15h	/
38	fix some bugs	simont	7972d 15h	/
37	added signals ack, stb and cyc	simont	7972d 15h	/
36	fix bugs in mode 0	simont	7972d 15h	/
35	design docunemt	simont	7973d 13h	/
34	specification docunemt	simont	7973d 13h	/
33	fix some bugs	simont	7973d 19h	/
32	overflow repaired	simont	7973d 19h	/
31	fix some bugs	simont	7980d 12h	/
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	7983d 18h	/
29	fix some bugs	simont	7983d 19h	/
28	remove syn signal	simont	7983d 19h	/
27	fix some bugs	simont	7983d 19h	/
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	7983d 21h	/