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37 This commit was manufactured by cvs2svn to create tag 'AEMB_7_05'. 6300d 18h /
36 Removed asynchronous reset signal. sybreon 6300d 18h /
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6301d 15h /
34 Corrected speed issues after rev 1.9 update. sybreon 6302d 04h /
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6317d 11h /
32 Modified compilation sequence. sybreon 6317d 11h /
31 Removed byte acrobatics. sybreon 6317d 11h /
30 Minor updates as sw/c/aeMB_testbench.c got updated. sybreon 6320d 12h /
29 Added code documentation.
Added new tests that test floating point, modulo arithmetic and multiplication/division.		 sybreon 6320d 12h /
28 Fixed simulation bug. sybreon 6320d 12h /
27 Removed some unnecessary bubble control. sybreon 6320d 23h /
26 Fixed minor synthesis bug. sybreon 6320d 23h /
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v		 sybreon 6321d 03h /
24 Made minor performance optimisations. sybreon 6321d 13h /
23 Fixed minor simulation bug. sybreon 6322d 04h /
22 Added support for 8-bit and 16-bit data types. sybreon 6322d 05h /
21 Added hierarchy block diagram. sybreon 6332d 10h /
20 Added basic documentation doc/aeMB_datasheet.pdf sybreon 6333d 00h /
19 Added initial unified memory core. sybreon 6334d 14h /
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6335d 07h /
17 Cosmetic changes sybreon 6336d 11h /
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.		 sybreon 6336d 23h /
15 Removed ROM file. Please generate it from the SW directory. sybreon 6343d 13h /
14 Added initial interrupt/exception support. sybreon 6343d 13h /
13 Fibonacci rom sybreon 6343d 21h /
12 Minor changes sybreon 6343d 21h /
11 Removed unused signals sybreon 6343d 21h /
10 Fixed minor bugs sybreon 6343d 21h /
9 Extended testbench code sybreon 6343d 21h /
8 Fixed memory read-write data hazard sybreon 6343d 21h /

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