OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] - Rev 70

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
70 The mlas_bug testcase tried to use stack without setting stack pointer
register, causing unpredictable behavoiur.
The patch uses an expilict stack area for the test.
Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>		 csantifort 4061d 12h /
69 Updated the spec for ISE 14.5, boot-loader-ethmac. csantifort 4061d 12h /
68 Remove modelsim files. Only supporting Xilinx isim now. csantifort 4061d 13h /
67 renamed boot-loader.c to boot-loader-serial.c csantifort 4061d 13h /
66 Remove the stand-alone ethmac test. Use boot-loader-ethmac instead to verify ethmac functionality. csantifort 4061d 13h /
65 Renamed boot-loader to boot-loader-serial csantifort 4061d 13h /
64 Support latest Xilinx ISE 14.5 software. csantifort 4061d 13h /
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.		 csantifort 4061d 18h /
62 Added source for amber-pkt2mem csantifort 4214d 06h /
61 Add new netowkr based boot loader.
Remove support for Virtex. Spartan 6 only now.		 csantifort 4348d 12h /
60 Bug fix; removed a combinational loop from the a25_decode logic. csantifort 4566d 08h /
59 Added modelsim script for reloading a wlf file after a simulation has been rerun. csantifort 4636d 06h /
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 4636d 09h /
57 Add some debug messages csantifort 4636d 09h /
56 Remove the timeouts file from svn. Its an output file and gets now just gets created automatically
when sims are run for the first time.		 csantifort 4636d 09h /
55 Added sudo to rm mnt command csantifort 4636d 09h /
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.		 csantifort 4653d 09h /
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4668d 07h /
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 4668d 07h /
51 Revert vmlinux back to 48. csantifort 4709d 07h /
50 Revert to previous version csantifort 4709d 07h /
49 Added a note n how to change timeouts csantifort 4709d 07h /
48 Fixed a bug in linux that caused the os to not return to the running application after an interrupt.
Hello-world now runs stand-alone again.
Added initrd-200k-dhry, a disk image that uses the dhry program for init.		 csantifort 4713d 13h /
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 4733d 11h /
46 svn ignore vmlinux.dis and vmlinux.mem csantifort 4741d 08h /
45 Store vmlinux.mem and vmlinux.dis in compressed form csantifort 4741d 09h /
44 Updated vmlinux image based on last change csantifort 4741d 09h /
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.		 csantifort 4741d 09h /
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 4759d 05h /
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 4760d 14h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.