URL https://opencores.org/ocsvn/apbi2c/apbi2c/trunk

Subversion Repositories apbi2c

[/] - Rev 24

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Rev	Log message	Author	Age	Path
24	Correcetd modules and back again toold plan on fifo using only registers.	redbear	3677d 23h	/
23	correcting TX FSM	redbear	3692d 05h	/
22	Correcting TX transmission and remove tri state from RTL.	redbear	3693d 00h	/
21	added tri state on module i2c	redbear	3706d 03h	/
20	Finished a previous version from RX and added SDA and SCL enable to PADS.	redbear	3706d 22h	/
19	changes about area use for proprely use.	redbear	3751d 22h	/
18	Corrected fifo mem acess, i2c_module and revised conections on top	redbear	3768d 22h	/
17	fifo.v and dual_port_ram.v	celaya.dario	3769d 22h	/
16	fifo.v and dual_port_ram.v	celaya.dario	3769d 22h	/
15	11'd1 to 4'd1	redbear	3776d 04h	/
14	added a and to make real full fifo.	redbear	3776d 05h	/
13	re write all fifo module to write and give full when the same is not full	redbear	3776d 05h	/
12	added PSELx on WR_ENA, RD_ENA to correct read/write when PSEL is HIGH	redbear	3776d 05h	/
11	Added configuration to define RX and TX operation and configure propely the ports.	redbear	3783d 01h	/
10	Correcting a few words wrote wrong.	redbear	3783d 01h	/
9	More description added on spec	redbear	3784d 02h	/
8	More description added on spec	redbear	3784d 03h	/
7	Corrected CLOCK generated by SCL according NXP spec.	redbear	3785d 03h	/
6	Adding a basic FSM to RX.	redbear	3790d 04h	/
5	Added about APB address necessary to read and write on FIFOS and register configuration.	redbear	3798d 01h	/
4	Added on module I2C basic error for register configuration	redbear	3798d 03h	/
3	Added a basic example on I2C Block.	redbear	3798d 03h	/
2	Adding files and initial version.	redbear	3798d 23h	/
1	The project and the structure was created	root	3801d 23h	/

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[/] - Rev 24

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