URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] - Rev 31

Rev	Log message	Author	Age	Path
31	test bench ongoing	wsong0210	4779d 01h	/
30	test bench cleaning up ongping	wsong0210	4780d 02h	/
29	begin the test environment	wsong0210	4781d 02h	/
28	merge the synthesis scripts in the branch init to trunk	wsong0210	4781d 02h	/
27	eliminate timing loops in all router architectures	wsong0210	4781d 03h	/
26	wormhole router compile OK	wsong0210	4782d 02h	/
25	resolve conflict	wsong0210	4782d 20h	/
24	make a branch	wsong0210	4782d 20h	/
23	try commit	wsong0210	4782d 21h	/
22	roll back	wsong0210	4782d 21h	/
21	prepare trunk	wsong0210	4782d 21h	/
20	prepare trunk	wsong0210	4782d 21h	/
19	sdm router ready	wsong0210	4783d 02h	/
18	allocators_modify	wsong0210	4784d 02h	/
17	allocators	wsong0210	4784d 02h	/
16	input buffers	wsong0210	4784d 03h	/
15	update license	wsong0210	4784d 22h	/
14	output buffers	wsong0210	4785d 02h	/
13	router structure configuration	wsong0210	4785d 02h	/
12	crossbars	wsong0210	4785d 02h	/
11	arbiters	wsong0210	4785d 04h	/
10	script for async cell lib disable timing arc	wsong0210	4787d 05h	/
9	cell library setting up script	wsong0210	4787d 19h	/
8	update the async cell lib	wsong0210	4787d 20h	/
7	add the verilog Nangate simulation file	wsong0210	4787d 20h	/
6	the asynchronous cell library	wsong0210	4787d 21h	/
5	modify the file dir for multiple designs	wsong0210	4787d 21h	/
4	update license and cell lib	wsong0210	4788d 02h	/
3	directories	wsong0210	4798d 19h	/
2	initial author list	wsong0210	4798d 19h	/