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URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

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Rev Log message Author Age Path
33 debug wsong0210 4815d 21h /
32 currently debugging the simulation compiling wsong0210 4816d 18h /
31 test bench ongoing wsong0210 4817d 18h /
30 test bench cleaning up ongping wsong0210 4818d 19h /
29 begin the test environment wsong0210 4819d 19h /
28 merge the synthesis scripts in the branch init to trunk wsong0210 4819d 19h /
27 eliminate timing loops in all router architectures wsong0210 4819d 20h /
26 wormhole router compile OK wsong0210 4820d 20h /
25 resolve conflict wsong0210 4821d 13h /
24 make a branch wsong0210 4821d 14h /
23 try commit wsong0210 4821d 14h /
22 roll back wsong0210 4821d 14h /
21 prepare trunk wsong0210 4821d 14h /
20 prepare trunk wsong0210 4821d 14h /
19 sdm router ready wsong0210 4821d 20h /
18 allocators_modify wsong0210 4822d 19h /
17 allocators wsong0210 4822d 19h /
16 input buffers wsong0210 4822d 20h /
15 update license wsong0210 4823d 15h /
14 output buffers wsong0210 4823d 19h /
13 router structure configuration wsong0210 4823d 19h /
12 crossbars wsong0210 4823d 20h /
11 arbiters wsong0210 4823d 21h /
10 script for async cell lib disable timing arc wsong0210 4825d 22h /
9 cell library setting up script wsong0210 4826d 12h /
8 update the async cell lib wsong0210 4826d 13h /
7 add the verilog Nangate simulation file wsong0210 4826d 13h /
6 the asynchronous cell library wsong0210 4826d 14h /
5 modify the file dir for multiple designs wsong0210 4826d 14h /
4 update license and cell lib wsong0210 4826d 19h /

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