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Rev	Log message	Author	Age	Path
130	mbist signals updated according to newest convention	markom	7528d 16h	/
129	Error counters changed.	mohor	7545d 01h	/
128	This commit was manufactured by cvs2svn to create tag 'rel_18'.		7545d 01h	/
127	Fixing the core to be Bosch VHDL Reference compatible.	mohor	7545d 01h	/
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7545d 21h	/
125	Synchronization changed, error counters fixed.	mohor	7550d 03h	/
124	ALTERA_RAM supported.	mohor	7570d 09h	/
123	This commit was manufactured by cvs2svn to create tag 'rel_17'.		7577d 15h	/
122	This commit was manufactured by cvs2svn to create tag 'rel_16'.		7577d 15h	/
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7577d 15h	/
120	This commit was manufactured by cvs2svn to create tag 'rel_15'.		7586d 12h	/
119	Artisan RAMs added.	mohor	7586d 12h	/
118	Artisan RAM fixed (when not using BIST).	mohor	7586d 12h	/
117	Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need to be joined together on higher level.	mohor	7586d 12h	/
116	This commit was manufactured by cvs2svn to create tag 'rel_14'.		7592d 06h	/
115	Artisan ram instances added.	simons	7592d 06h	/
114	This commit was manufactured by cvs2svn to create tag 'rel_13'.		7619d 07h	/
113	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7619d 07h	/
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7619d 07h	/
111	Fixed according to the linter. Case statement for data_out joined.	mohor	7621d 07h	/
110	Fixed according to the linter.	mohor	7621d 07h	/
109	Fixed according to the linter.	mohor	7621d 08h	/
108	Fixed according to the linter.	mohor	7621d 08h	/
107	Fixed according to the linter.	mohor	7621d 09h	/
106	Unused signal removed.	mohor	7627d 07h	/
105	This commit was manufactured by cvs2svn to create tag 'rel_11'.		7627d 20h	/
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7627d 20h	/
103	This commit was manufactured by cvs2svn to create tag 'complete_1'.		7630d 11h	/
102	Little fixes (to fix warnings).	mohor	7630d 11h	/
101	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7634d 13h	/

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