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Rev	Log message	Author	Age	Path
148	This commit was manufactured by cvs2svn to create tag 'rel_23'.		7171d 23h	/
147	Interrupt is always cleared for one clock after the irq register is read. This fixes problems when CPU is using IRQs that are edge triggered.	igorm	7171d 23h	/
146	This commit was manufactured by cvs2svn to create tag 'rel_22'.		7172d 04h	/
145	Arbitration bug fixed.	igorm	7172d 04h	/
144	This commit was manufactured by cvs2svn to create tag 'rel_21'.		7318d 20h	/
143	Bit acceptance_filter_mode was inverted.	igorm	7318d 20h	/
142	This commit was manufactured by cvs2svn to create tag 'rel_20'.		7337d 19h	/
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7337d 19h	/
140	I forgot to thange one signal name.	igorm	7392d 17h	/
139	Signal bus_off_on added.	igorm	7392d 18h	/
138	Header changed. Address latched to posedge. bus_off_on signal added.	mohor	7431d 20h	/
137	Header changed.	mohor	7431d 20h	/
136	Error counters changed.	mohor	7431d 20h	/
135	Header changed.	mohor	7431d 21h	/
134	Active high/low problem when Altera devices are used. Bug fixed by Rojhalat Ibrahim.	mohor	7539d 18h	/
133	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7546d 05h	/
132	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7546d 05h	/
131	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7546d 05h	/
130	mbist signals updated according to newest convention	markom	7546d 05h	/
129	Error counters changed.	mohor	7562d 14h	/
128	This commit was manufactured by cvs2svn to create tag 'rel_18'.		7562d 14h	/
127	Fixing the core to be Bosch VHDL Reference compatible.	mohor	7562d 14h	/
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7563d 10h	/
125	Synchronization changed, error counters fixed.	mohor	7567d 16h	/
124	ALTERA_RAM supported.	mohor	7587d 22h	/
123	This commit was manufactured by cvs2svn to create tag 'rel_17'.		7595d 04h	/
122	This commit was manufactured by cvs2svn to create tag 'rel_16'.		7595d 04h	/
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7595d 04h	/
120	This commit was manufactured by cvs2svn to create tag 'rel_15'.		7604d 01h	/
119	Artisan RAMs added.	mohor	7604d 01h	/

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