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Rev Log message Author Age Path
76 Counters width changed. mohor 7725d 01h /
75 When switching to tx, sync stage is overjumped. mohor 7727d 02h /
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7727d 06h /
73 overrun and length_info fifos are initialized at the end of reset. mohor 7727d 06h /
72 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7729d 05h /
71 Ports added for the CAN_BIST. mohor 7729d 05h /
70 data_out is already registered in the can_top.v file. mohor 7729d 05h /
69 Some features are supported in extended mode only (listen_only_mode...). mohor 7784d 01h /
68 CAN inturrupt is active low. mohor 7804d 05h /
67 CAN interrupt is active low. mohor 7804d 05h /
66 unix. mohor 7809d 23h /
65 unix. mohor 7809d 23h /
64 *** empty log message *** mohor 7809d 23h /
63 ALE changes on negedge of clk. mohor 7815d 20h /
62 can_cs signal used for generation of the cs. mohor 7815d 20h /
61 Bidirectional port_0_i changed to port_0_io.
input cs_can changed to cs_can_i.
mohor 7818d 10h /
60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.
mohor 7818d 11h /
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.
mohor 7818d 12h /
58 timescale.v is used for simulation only. mohor 7819d 00h /
57 Mux used for clkout to avoid "gated clocks warning". mohor 7819d 00h /
56 Doubled declarations removed. mohor 7819d 22h /
55 wire declaration added. mohor 7819d 23h /
54 This commit was manufactured by cvs2svn to create tag 'branch-release-1-0'. 7825d 00h /
53 CAN pins located. mohor 7825d 00h /
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7825d 01h /
51 Xilinx RAM added. mohor 7825d 01h /
50 Top level signal names changed. mohor 7825d 01h /
49 Actel APA ram changed. Now synchronous read is used. mohor 7828d 17h /
48 Actel APA ram supported. mohor 7828d 17h /
47 Data is latched on read. mohor 7828d 17h /

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