URL https://opencores.org/ocsvn/common/common/trunk

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[/] - Rev 27

Rev	Log message	Author	Age	Path
27	no message	bbeaver	8277d 22h	/
26	no message	bbeaver	8278d 21h	/
25	no message	bbeaver	8279d 23h	/
24	no message	bbeaver	8282d 00h	/
23	no message	bbeaver	8282d 23h	/
22	no message	bbeaver	8283d 03h	/
21	Added bookmarks.	lampret	8283d 16h	/
20	Some minor fixes. Document is now official version.	lampret	8283d 17h	/
19	no message	bbeaver	8285d 00h	/
18	no message	bbeaver	8285d 22h	/
17	Fixed link to specification_template.dot	lampret	8286d 07h	/
16	Added updated opencores coding guidelines. Added ver_plan.pdf and Specification template for Word.	lampret	8286d 08h	/
15	no message	bbeaver	8306d 05h	/
14	adding beginning LPM files	bbeaver	8318d 01h	/
13	This commit was manufactured by cvs2svn to create tag 'initial'.		8324d 01h	/
12	Major cleanup. Files are now compliant to Altera & Xilinx memories. Memories are now compatible, i.e. drop-in replacements. Added synthesizeable generic FPGA description. Created "generic_memories" cvs entry.	rherveille	8324d 01h	/
11	no message	bbeaver	8330d 23h	/
10	no message	bbeaver	8330d 23h	/
9	no message	bbeaver	8334d 21h	/
8	no message	bbeaver	8334d 22h	/
7	no message	bbeaver	8334d 22h	/
6	no message	bbeaver	8334d 23h	/
5	no message	bbeaver	8334d 23h	/
4	no message	bbeaver	8334d 23h	/
3	This commit was manufactured by cvs2svn to create tag 'arelease'.		8335d 00h	/
2	no message	bbeaver	8335d 00h	/
1	Standard project directories initialized by cvs2svn.		8335d 00h	/