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Rev Log message Author Age Path
40 Updated PDF. lampret 7984d 08h /
39 Added Richard's feedback. lampret 7986d 08h /
38 Undeleted mohor 8006d 22h /
37 no message bbeaver 8243d 04h /
36 minor changes: unified with all common rams samg 8263d 13h /
35 corrected output: output not valid if ce low samg 8263d 18h /
34 added valid checks to behvioral model samg 8263d 18h /
33 added checks and task in behavioral section samg 8264d 19h /
32 no message bbeaver 8266d 01h /
31 no message bbeaver 8270d 01h /
30 no message bbeaver 8271d 00h /
29 got timing checks mostly correct
No functional stuff yet		 bbeaver 8271d 01h /
28 no message bbeaver 8272d 01h /
27 no message bbeaver 8273d 01h /
26 no message bbeaver 8273d 23h /
25 no message bbeaver 8275d 01h /
24 no message bbeaver 8277d 03h /
23 no message bbeaver 8278d 02h /
22 no message bbeaver 8278d 05h /
21 Added bookmarks. lampret 8278d 18h /
20 Some minor fixes. Document is now official version. lampret 8278d 19h /
19 no message bbeaver 8280d 03h /
18 no message bbeaver 8281d 01h /
17 Fixed link to specification_template.dot lampret 8281d 09h /
16 Added updated opencores coding guidelines. Added ver_plan.pdf and Specification template for Word. lampret 8281d 10h /
15 no message bbeaver 8301d 07h /
14 adding beginning LPM files bbeaver 8313d 03h /
13 This commit was manufactured by cvs2svn to create tag 'initial'. 8319d 03h /
12 Major cleanup.
Files are now compliant to Altera & Xilinx memories.
Memories are now compatible, i.e. drop-in replacements.
Added synthesizeable generic FPGA description.
Created "generic_memories" cvs entry.		 rherveille 8319d 03h /
11 no message bbeaver 8326d 01h /

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