OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 67

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
67 Lower two address lines must be always zero. simons 7621d 14h /
66 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7622d 13h /
65 WB_CNTL register added, some syncronization fixes. simons 7622d 13h /
64 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7642d 14h /
63 Three more chains added for cpu debug access. simons 7642d 14h /
62 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7670d 14h /
61 Lapsus fixed. simons 7670d 14h /
60 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7670d 14h /
59 Reset value for riscsel register set to 1. simons 7670d 14h /
58 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7670d 15h /
57 Multiple cpu support added. simons 7670d 15h /
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.
mohor 7937d 12h /
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.
mohor 7937d 12h /
54 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7937d 13h /
53 Trst active high. Inverted on higher layer. mohor 7937d 13h /
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7937d 13h /
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7965d 01h /
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 7965d 02h /
49 This commit was manufactured by cvs2svn to create tag 'sdram_test_working'. 8120d 13h /
48 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8120d 13h /
47 mon_cntl_o signals that controls monitor mux added. mohor 8120d 13h /
46 Asynchronous reset used instead of synchronous. mohor 8128d 19h /
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8135d 15h /
44 Signal names changed to lower case. mohor 8135d 15h /
43 Intentional error removed. mohor 8140d 15h /
42 A block for checking possible simulation/synthesis missmatch added. mohor 8140d 17h /
41 Function changed to logic because of some synthesis warnings. mohor 8148d 13h /
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8162d 13h /
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.
mohor 8163d 15h /
38 Few outputs for boundary scan chain added. mohor 8176d 13h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.