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Rev Log message Author Age Path
71 Mbist support added. simons 7625d 17h /
70 A pdf copy of existing doc document. simons 7632d 18h /
69 WBCNTL added, multiple CPU support described. simons 7653d 08h /
68 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7658d 12h /
67 Lower two address lines must be always zero. simons 7658d 12h /
66 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7659d 12h /
65 WB_CNTL register added, some syncronization fixes. simons 7659d 12h /
64 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7679d 12h /
63 Three more chains added for cpu debug access. simons 7679d 12h /
62 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7707d 12h /
61 Lapsus fixed. simons 7707d 12h /
60 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7707d 13h /
59 Reset value for riscsel register set to 1. simons 7707d 13h /
58 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7707d 14h /
57 Multiple cpu support added. simons 7707d 14h /
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7974d 10h /
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7974d 10h /
54 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7974d 12h /
53 Trst active high. Inverted on higher layer. mohor 7974d 12h /
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7974d 12h /
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 8002d 00h /
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 8002d 00h /
49 This commit was manufactured by cvs2svn to create tag 'sdram_test_working'. 8157d 12h /
48 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8157d 12h /
47 mon_cntl_o signals that controls monitor mux added. mohor 8157d 12h /
46 Asynchronous reset used instead of synchronous. mohor 8165d 18h /
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8172d 13h /
44 Signal names changed to lower case. mohor 8172d 13h /
43 Intentional error removed. mohor 8177d 13h /
42 A block for checking possible simulation/synthesis missmatch added. mohor 8177d 15h /

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