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Rev	Log message	Author	Age	Path
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8268d 08h	/
28	New release. Name changed to lower case.	mohor	8271d 00h	/
27	File names changed to lower case.	mohor	8271d 00h	/
26	First release of product brief.	mohor	8271d 00h	/
25	First release of product brief.	mohor	8271d 00h	/
24	Log file added.	mohor	8293d 11h	/
23	Number of addresses (wb_adr_i) minimized.	mohor	8293d 11h	/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8293d 14h	/
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8294d 11h	/
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8318d 08h	/
19	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8318d 08h	/
18	Few little NCSIM warnings fixed.	mohor	8331d 09h	/
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8358d 09h	/
16	"else" was missing within the always block in file eth_wishbonedma.v.	mohor	8365d 14h	/
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8367d 08h	/
14	Unconnected signals are now connected.	mohor	8371d 13h	/
13	New directory structure. Files upodated and put together.	mohor	8373d 22h	/
12	Directory structure changed. Files checked and joind together.	mohor	8374d 01h	/
11	Directory structure changed. Files checked and joind together.	mohor	8374d 01h	/
10	Directory structure changed. Files checked and joind together.	mohor	8374d 01h	/
9	Documentation updated to be synchronized to the verilog files.	mohor	8401d 10h	/
8	Version 1.3. Status registers added. DMA channels 2 and 3 are not used any more. Things that are implementation specific were deleted out of the document.	mohor	8428d 15h	/
7	Version 1.3. Status registers added. DMA channels 2 and 3 are not used any more. Things that are implementation specific were deleted out of the document.	mohor	8428d 15h	/
6	no message	mohor	8428d 15h	/
5	This is a Microsoft version of the spec in the pdf format.	mohor	8433d 00h	/
4	deleted	mohor	8433d 00h	/
3	This commit was manufactured by cvs2svn to create tag 'arelease'.		8505d 01h	/
2	no message	mohor	8505d 01h	/
1	Standard project directories initialized by cvs2svn.		8505d 01h	/

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