URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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Rev	Log message	Author	Age	Path
50	checks destination address for Unicast, Multicast and Broadcast ops	billditt	8194d 03h	/
49	HASH0 and HASH1 register read/write added.	mohor	8196d 02h	/
48	RxOverRun added to statuses.	mohor	8196d 05h	/
47	HASH0 and HASH1 registers added. Registers address width was changed to 8 bits.	mohor	8196d 05h	/
46	HASH0 and HASH1 registers added.	mohor	8196d 05h	/
45	Ethernet Datasheet added.	mohor	8196d 12h	/
44	Ethernet Datasheet added to cvs.	mohor	8196d 12h	/
43	Tx status is written back to the BD.	mohor	8197d 13h	/
42	Rx status is written back to the BD.	mohor	8200d 06h	/
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8202d 08h	/
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8203d 06h	/
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8207d 10h	/
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8216d 12h	/
37	Link in the header changed.	mohor	8216d 12h	/
36	TX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8262d 10h	/
35	RX_BD_NUM changed to TX_BD_NUM. Few typos corrected.	mohor	8265d 07h	/
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8265d 07h	/
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8265d 12h	/
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8265d 12h	/
31	RX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8265d 12h	/
30	BD section updated.	mohor	8267d 09h	/
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8287d 08h	/
28	New release. Name changed to lower case.	mohor	8289d 23h	/
27	File names changed to lower case.	mohor	8289d 23h	/
26	First release of product brief.	mohor	8290d 00h	/
25	First release of product brief.	mohor	8290d 00h	/
24	Log file added.	mohor	8312d 11h	/
23	Number of addresses (wb_adr_i) minimized.	mohor	8312d 11h	/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8312d 14h	/
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8313d 10h	/

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