URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

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Rev	Log message	Author	Age	Path
44	no message	fisher5090	6629d 11h	/
43	no message	fisher5090	6629d 15h	/
42	no message	fisher5090	6629d 15h	/
41	no message	fisher5090	6629d 15h	/
40	This commit was manufactured by cvs2svn to create tag 'V10'.		6635d 14h	/
39	first version	fisher5090	6635d 14h	/
38	deleted	fisher5090	6635d 15h	/
37	no message	fisher5090	6635d 15h	/
36	no message	godzilla	6699d 00h	/
35	no message	godzilla	6701d 23h	/
34	Rewritten code.	godzilla	6701d 23h	/
33	Rewritten code.	godzilla	6702d 00h	/
32	no message	fisher5090	6719d 08h	/
31	no message	fisher5090	6719d 08h	/
30	no message	fisher5090	6747d 07h	/
29	no message	fisher5090	6747d 16h	/
28	First commit. 32-bit counter. Synthesizes with no errors in Xilinx XST.	mvpratt	6750d 02h	/
27	xilinx coregen	fisher5090	6760d 07h	/
26	good edition	fisher5090	6760d 07h	/
25	no message	fisher5090	6760d 07h	/
24	First cut. One of the main culprits for the timing violations.	godzilla	6762d 23h	/
23	First cut. Original code from Easic but add some extra controls. One of the main culprits for the timing violations.	godzilla	6762d 23h	/
22	First cut. Original code from Easic but add some extra controls.	godzilla	6762d 23h	/
21	First cut. Not thoroughly tested yet but still need to implement the configuration, non-crc version and stats. So far Leonardo Precison indicates the design can run upto 101 MHz but need to remove the timing violations to increase speed.	godzilla	6762d 23h	/
20	First cut. Still need to update the document with design changes.	godzilla	6762d 23h	/
19	First cut.	godzilla	6762d 23h	/
18	works well	fisher5090	6767d 12h	/
17	crc test	fisher5090	6767d 19h	/
16	use counter	fisher5090	6771d 03h	/
15	crc module	fisher5090	6771d 03h	/

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Subversion Repositories ethmac10g

[/] - Rev 44

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