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Subversion Repositories ha1588

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Rev	Log message	Author	Age	Path
37	Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit	edn_walter	4470d 10h	/
36	TSU testbench is now self-checking. Test result is reported at end of simulation.	edn_walter	4471d 05h	/
35	Added support for stacked MPLS UDP/IPv4/IPv6 PTP packets.	edn_walter	4472d 04h	/
34	Added LGPL file header to all copyrighted files.	edn_walter	4472d 07h	/
33	Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules.	edn_walter	4472d 08h	/
32	Added PTP standard time format output to the top module. Can be connected to external modules.	edn_walter	4472d 10h	/
31	Added hand-shaking for the TSU data reading.	edn_walter	4473d 04h	/
30	Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit	edn_walter	4473d 04h	/
29	Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz.	edn_walter	4473d 04h	/
28	Before changing TSU packet parser datapath width from 32b to 8b.	edn_walter	4473d 10h	/
27	Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s.	edn_walter	4473d 10h	/
26	Updated test case.	edn_walter	4475d 05h	/
25	Updated SOPC Builder component and example system.	edn_walter	4476d 04h	/
24	Added test cases for top-level testbench to cover both RTC and TSU.	edn_walter	4476d 05h	/
23	Added CDC hand-shaking for RTC time reading operation.	edn_walter	4476d 23h	/
22	RTC reset will clear ACC counter, but not clear ACC counter incremental.	edn_walter	4477d 04h	/
21	Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application.	edn_walter	4478d 00h	/
20	Added SOPC Builder Component and Instantiation Example. Follow rtl/sopc/ReadMe.txt to add IP Search Path to SOPC Builder.	edn_walter	4482d 04h	/
19	Added pipeline registers to Real Time Clock module to improve timing.	edn_walter	4482d 04h	/
18	Added QuartusII Place and Route project for top level ha1588.v	edn_walter	4482d 04h	/
17	Updated reg.v content.	edn_walter	4482d 22h	/
16	Try to add sth.	edn_walter	4486d 15h	/
15	Renamed module name for tsu and rtc. Added folder for reg and top. Added folder for sopc, preparing for Altera SOPC Builder customized component.	edn_walter	4489d 00h	/
14	Added test case support for UDP/IPv6 PTP frames.	edn_walter	4491d 00h	/
13	Added test case support for single VLAN and double VLAN L2/L4 PTP frames.	edn_walter	4492d 00h	/
12	Added parser support for vlan tagged frames.	edn_walter	4492d 22h	/
11	Added parser support for L2_PTP and IPv4/v6_UDP_PTP frame formats.	edn_walter	4493d 23h	/
10	Added parser support for L2_PTP and IPv4_UDP_PTP frame formats.	edn_walter	4495d 00h	/
9	Timestamp format in the queue = seqId_16bit + msgId_4bit + timeStamp1s_2bit + timeStamp1ns_30bit	edn_walter	4495d 23h	/
8	Timestamp format in the queue = seqId_16bit + msgId_2bit + timeStamp_30bit	edn_walter	4496d 06h	/

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