URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] - Rev 21

Rev	Log message	Author	Age	Path
21	no message	rherveille	8115d 09h	/
20	Added Appendix A	rherveille	8115d 09h	/
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8119d 05h	/
18	no message	rherveille	8146d 01h	/
17	C-include file. Initial release	rherveille	8234d 06h	/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8246d 05h	/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8251d 04h	/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8251d 04h	/
13	Fixed some synthesis warnings.	rherveille	8262d 08h	/
12	no message	rherveille	8267d 23h	/
11	Changed RST_LVL define to parameter.	rherveille	8271d 07h	/
10	Created new directory structure. Added Verilog version.	rherveille	8293d 03h	/
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8362d 22h	/
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8362d 23h	/
7	added some remarks, fixed some sensitivity lists	rherveille	8432d 01h	/
6	fixed typo txt -> txr	rherveille	8436d 05h	/
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8443d 03h	/
4	WISHBONE I2C Master Core: initial release	rherveille	8495d 06h	/
3	This commit was manufactured by cvs2svn to create tag 'first'.		8557d 06h	/
2	initial release	rherveille	8557d 06h	/
1	Standard project directories initialized by cvs2svn.		8557d 06h	/