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Rev Log message Author Age Path
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7900d 07h /
23 *** empty log message *** rherveille 8027d 13h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8037d 18h /
21 no message rherveille 8123d 18h /
20 Added Appendix A rherveille 8123d 18h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 8127d 15h /
18 no message rherveille 8154d 11h /
17 C-include file.
Initial release
rherveille 8242d 15h /
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8254d 14h /
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 8259d 13h /
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 8259d 13h /
13 Fixed some synthesis warnings. rherveille 8270d 17h /
12 no message rherveille 8276d 09h /
11 Changed RST_LVL define to parameter. rherveille 8279d 16h /
10 Created new directory structure.
Added Verilog version.
rherveille 8301d 13h /
9 Created directory structure (documentation, vhdl, verilog) rherveille 8371d 08h /
8 Created directory structure (documentation, vhdl, verilog) rherveille 8371d 08h /
7 added some remarks, fixed some sensitivity lists rherveille 8440d 11h /
6 fixed typo txt -> txr rherveille 8444d 14h /
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8451d 13h /
4 WISHBONE I2C Master Core: initial release rherveille 8503d 16h /
3 This commit was manufactured by cvs2svn to create tag 'first'. 8565d 15h /
2 initial release rherveille 8565d 15h /
1 Standard project directories initialized by cvs2svn. 8565d 15h /

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