URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

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Rev	Log message	Author	Age	Path
25	Added timing tests to i2c_model. Updated testbench.	rherveille	7879d 03h	/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7879d 03h	/
23	* empty log message *	rherveille	8006d 08h	/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8016d 13h	/
21	no message	rherveille	8102d 14h	/
20	Added Appendix A	rherveille	8102d 14h	/
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8106d 10h	/
18	no message	rherveille	8133d 06h	/
17	C-include file. Initial release	rherveille	8221d 11h	/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8233d 10h	/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8238d 09h	/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8238d 09h	/
13	Fixed some synthesis warnings.	rherveille	8249d 13h	/
12	no message	rherveille	8255d 04h	/
11	Changed RST_LVL define to parameter.	rherveille	8258d 12h	/
10	Created new directory structure. Added Verilog version.	rherveille	8280d 08h	/
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8350d 03h	/
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8350d 04h	/
7	added some remarks, fixed some sensitivity lists	rherveille	8419d 06h	/
6	fixed typo txt -> txr	rherveille	8423d 10h	/
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8430d 08h	/
4	WISHBONE I2C Master Core: initial release	rherveille	8482d 11h	/
3	This commit was manufactured by cvs2svn to create tag 'first'.		8544d 11h	/
2	initial release	rherveille	8544d 11h	/
1	Standard project directories initialized by cvs2svn.		8544d 11h	/

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Subversion Repositories i2c

[/] - Rev 25

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