Rev |
Log message |
Author |
Age |
Path |
170 |
Fixed bug in optional emulation of EXT, INS |
ja_rd |
4831d 23h |
/ |
169 |
Fixed bug in emulation of CLO instruction
Added support for simulated hardware IRQs (incomplete) |
ja_rd |
4831d 23h |
/ |
168 |
Updated 'opcodes' simulation script to NOT use simulated mips32 instructions and trap instead (as the real CPU does) |
ja_rd |
4831d 23h |
/ |
167 |
Updated simulation script for 'hello' sample: now uses function call log.
It is useless in this demo, but it shows how to use it. |
ja_rd |
4832d 00h |
/ |
166 |
Modified simulator, added some debug functionality:
- Optional emulation of some MIPS32r2 opcodes
- Function call trace log using map file (crude implementation)
Plus a few small bug fixes |
ja_rd |
4832d 00h |
/ |
165 |
Added (very early draft, very incomplete) reserved opcode trap handler.
Updated opcode tester to test some emulated mips32 opcodes using the trap handler. |
ja_rd |
4837d 09h |
/ |
164 |
Minor typo fixes in source file |
ja_rd |
4837d 09h |
/ |
163 |
SW simulator update:
Better disassembly format (hastily tested)
New parameters: start address, breakpoint address, whether or not to trap reserved opcodes |
ja_rd |
4837d 10h |
/ |
162 |
Fixed stupid mistake in headers (date of project) |
ja_rd |
4838d 01h |
/ |
161 |
Added GPL license info to the vhdl headers
This project is becoming respectable :) |
ja_rd |
4838d 01h |
/ |
160 |
BUG FIX: the cache init code was messing the BSS initialization |
ja_rd |
4839d 03h |
/ |
159 |
bug detected but not fixed in cpu
(1st instruction after entering user mode is executed in kernel mode) |
ja_rd |
4839d 10h |
/ |
158 |
removed file from TB directory which was committed by mistake |
ja_rd |
4839d 10h |
/ |
157 |
Bug fix in the missing coprocesor exception.
The CPU was triggering a privilege exception for the mtc0 that went into user mode.
Logging HDL updated |
ja_rd |
4840d 20h |
/ |
156 |
project doc somewhat updated (but still out of date) |
ja_rd |
4841d 03h |
/ |
155 |
Temporary warning added to outdated project doc file |
ja_rd |
4841d 04h |
/ |
154 |
fixed log trigger address in hello makefile |
ja_rd |
4841d 05h |
/ |
153 |
Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator
Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it. |
ja_rd |
4841d 05h |
/ |
152 |
Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator
Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it. |
ja_rd |
4841d 05h |
/ |
151 |
BUG FIX: major bugs fixed in cache module
1.- sram address was wrong (leftover from previous version)
2.- writes to unmapped areas were blocking the cache
3.- Sequence SW,LW produced a RAW data hazard in some cases |
ja_rd |
4841d 05h |
/ |
150 |
Bug fix: added missing nop in vacant branch delay slot |
ja_rd |
4842d 03h |
/ |
149 |
changed size of simulated flash in opcodes sample code |
ja_rd |
4842d 03h |
/ |
148 |
Added optional cache support to 'opcodes' test.
Updated simulation length accordingly. |
ja_rd |
4843d 18h |
/ |
147 |
SW simulator updated to latest HW revision
(plus a few mistakes corrected: wrongly commented out lines, mostly) |
ja_rd |
4843d 18h |
/ |
146 |
Added D-Cache setup code to 'adventure' bootstrap code
(redundant since common C startup code already does it but...) |
ja_rd |
4843d 19h |
/ |
145 |
MAJOR UPDATE: first version of D-Cache |
ja_rd |
4843d 19h |
/ |
144 |
Added cache setup code to common startup code
Important: the new cache won't work without this |
ja_rd |
4843d 19h |
/ |
143 |
'adventure' sample by default will log from 0xb0000000
and simulation length is now longer |
ja_rd |
4845d 09h |
/ |
142 |
'Adventure' bootstrap code now enables the cache
(and runs noticeably faster on DE-1 board) |
ja_rd |
4845d 09h |
/ |
141 |
BUG FIX in cache: cpu stall logic was missing key case
2nd SW in a (cached) row was not being stalled |
ja_rd |
4845d 09h |
/ |