| Rev |
Log message |
Author |
Age |
Path |
| 178 |
Added FP math support to support library
Uses code lifted from old version of GNU libc, no adaptation needed
NEEDS testing! |
ja_rd |
4776d 13h |
/ |
| 177 |
Modified 'Adventure' demo to use new support code |
ja_rd |
4776d 13h |
/ |
| 176 |
Modified 'hello' to use new support code
NOTE: the 'OPCODE EMULATOR' mentioned below is the TRAP HANDLER
The SW opcode emulation has been working for months |
ja_rd |
4776d 13h |
/ |
| 175 |
Updated support library
Removed spurious dependence to accursed '_impure_ptr' |
ja_rd |
4776d 14h |
/ |
| 174 |
started to add branch emulation to opcode emulator |
ja_rd |
4776d 14h |
/ |
| 173 |
New version of support code, still incomplete. |
ja_rd |
4776d 14h |
/ |
| 172 |
Added new version of support code, still incomplete |
ja_rd |
4778d 04h |
/ |
| 171 |
CPU bug fix: MFC0 instructions aborted by privilege trap should not modify any register |
ja_rd |
4779d 07h |
/ |
| 170 |
Fixed bug in optional emulation of EXT, INS |
ja_rd |
4779d 17h |
/ |
| 169 |
Fixed bug in emulation of CLO instruction
Added support for simulated hardware IRQs (incomplete) |
ja_rd |
4779d 17h |
/ |
| 168 |
Updated 'opcodes' simulation script to NOT use simulated mips32 instructions and trap instead (as the real CPU does) |
ja_rd |
4779d 17h |
/ |
| 167 |
Updated simulation script for 'hello' sample: now uses function call log.
It is useless in this demo, but it shows how to use it. |
ja_rd |
4779d 18h |
/ |
| 166 |
Modified simulator, added some debug functionality:
- Optional emulation of some MIPS32r2 opcodes
- Function call trace log using map file (crude implementation)
Plus a few small bug fixes |
ja_rd |
4779d 18h |
/ |
| 165 |
Added (very early draft, very incomplete) reserved opcode trap handler.
Updated opcode tester to test some emulated mips32 opcodes using the trap handler. |
ja_rd |
4785d 03h |
/ |
| 164 |
Minor typo fixes in source file |
ja_rd |
4785d 03h |
/ |
| 163 |
SW simulator update:
Better disassembly format (hastily tested)
New parameters: start address, breakpoint address, whether or not to trap reserved opcodes |
ja_rd |
4785d 04h |
/ |
| 162 |
Fixed stupid mistake in headers (date of project) |
ja_rd |
4785d 19h |
/ |
| 161 |
Added GPL license info to the vhdl headers
This project is becoming respectable :) |
ja_rd |
4785d 19h |
/ |
| 160 |
BUG FIX: the cache init code was messing the BSS initialization |
ja_rd |
4786d 21h |
/ |
| 159 |
bug detected but not fixed in cpu
(1st instruction after entering user mode is executed in kernel mode) |
ja_rd |
4787d 04h |
/ |
| 158 |
removed file from TB directory which was committed by mistake |
ja_rd |
4787d 04h |
/ |
| 157 |
Bug fix in the missing coprocesor exception.
The CPU was triggering a privilege exception for the mtc0 that went into user mode.
Logging HDL updated |
ja_rd |
4788d 14h |
/ |
| 156 |
project doc somewhat updated (but still out of date) |
ja_rd |
4788d 21h |
/ |
| 155 |
Temporary warning added to outdated project doc file |
ja_rd |
4788d 22h |
/ |
| 154 |
fixed log trigger address in hello makefile |
ja_rd |
4788d 23h |
/ |
| 153 |
Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator
Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it. |
ja_rd |
4788d 23h |
/ |
| 152 |
Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator
Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it. |
ja_rd |
4788d 23h |
/ |
| 151 |
BUG FIX: major bugs fixed in cache module
1.- sram address was wrong (leftover from previous version)
2.- writes to unmapped areas were blocking the cache
3.- Sequence SW,LW produced a RAW data hazard in some cases |
ja_rd |
4788d 23h |
/ |
| 150 |
Bug fix: added missing nop in vacant branch delay slot |
ja_rd |
4789d 21h |
/ |
| 149 |
changed size of simulated flash in opcodes sample code |
ja_rd |
4789d 21h |
/ |
