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Rev	Log message	Author	Age	Path
59	cleaned up top vhdl module of demo moved reset sync ff chain to top module updated pre-generated demo file	ja_rd	4911d 14h	/
58	Cleaned up cache stub code	ja_rd	4912d 01h	/
57	updated precompiled demo: single 32-bit BROM instead of 4x8-bit	ja_rd	4912d 03h	/
56	synthesis mpu template updated: BRAM is now one 32-bit-wide block instead of 4 8-bitters (it is read only) python script updated accordingly	ja_rd	4912d 03h	/
55	First version of cache: stub, 1-word cache (forgot to commit new mpu template file)	ja_rd	4912d 03h	/
54	Doc updated Cache section (2.7) is still missing	ja_rd	4912d 06h	/
53	SW simulator: Major change in logging code. Changes are logged now with the address of the instruction that caused them. These changes make the HW simulation TB's life easier.	ja_rd	4912d 06h	/
52	Sim scripts adapted to recent changes	ja_rd	4912d 06h	/
51	Adapted simulation and synth templates for cache module	ja_rd	4912d 06h	/
50	New code sample: memtest Tests external RAM	ja_rd	4912d 06h	/
49	'hello' demo: updated to use new cache module No longer uses temporary hacks or custom linker script	ja_rd	4912d 07h	/
48	Temporary fix to memory decoding constants	ja_rd	4912d 07h	/
47	Pre-generated simulation test benches updated	ja_rd	4912d 07h	/
46	First version of cache: stub, 1-word cache Stub cache tested on simulation and HW, just a stub Adapted CPU stall logic to 1st version of cache Adapted all other modules for compatibility with cache	ja_rd	4912d 07h	/
45	Fixed some typos in the main doc	ja_rd	4914d 02h	/
44	slite: cleaned up memory allocation/deallocation code	ja_rd	4914d 11h	/
43	added comments to dummy 'cache' stub	ja_rd	4914d 14h	/
42	Added cache stub module, plus related test bench	ja_rd	4916d 09h	/
41	Updated main project doc	ja_rd	4916d 09h	/
40	pre-generated 'hello' demo updated	ja_rd	4916d 09h	/
39	Updated main project doc	ja_rd	4916d 09h	/
38	Minor changes in header comments	ja_rd	4916d 10h	/
37	functions added to package for standard address decoding	ja_rd	4916d 10h	/
36	pre-generated simulation test bench TB1 updated for compatibility to other changes	ja_rd	4916d 10h	/
35	CPU mem_wait logic updated to work with cache	ja_rd	4916d 10h	/
34	default data address moved to 0x80000000 makefiles and readme files updated accordingly	ja_rd	4916d 10h	/
33	bin2hdl now can initialize 16-bit wide memories	ja_rd	4916d 10h	/
32	slite: catch 1-instruction endless loops now can run unattended; will stop at the end of main()	ja_rd	4916d 11h	/
31	Major refactor in slite: supports memory map with more than 1 block indentation made homogeneous unused code removed	ja_rd	4916d 11h	/
30	Completed decoding of instructions (to prevent side effects of invalid opcodes)	ja_rd	4918d 07h	/

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