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Rev Log message Author Age Path
48 Added proper carry generation inside ALU fafa1971 5622d 19h /
47 Updated TODO list fafa1971 5624d 22h /
46 Added again System Configuration Registers to properly handle exceptions. fafa1971 5624d 22h /
45 Useless files fafa1971 5698d 19h /
44 New top-level for Spartan-3E Starter Kit fafa1971 5698d 20h /
43 New filelists fafa1971 5698d 20h /
42 New tests fafa1971 5698d 20h /
41 New scripts fafa1971 5698d 20h /
40 This code is not needed anymore fafa1971 5698d 20h /
39 Moved boot code and functional verification tests into subdirs fafa1971 5698d 20h /
38 Deleted obsolete files. fafa1971 5698d 20h /
37 New scripts for a new Mistral world fafa1971 5698d 20h /
36 Added new behavioral stuff for Wishbone peripherals fafa1971 5698d 20h /
35 New testbench with Wishbone peripherals fafa1971 5698d 20h /
34 Added all the new files for Wishbone peripherals fafa1971 5698d 20h /
33 Added files from Mistral's new world fafa1971 5698d 20h /
32 Moved files from m1_cpu to m1_core dir fafa1971 5698d 20h /
31 New world for Mistral fafa1971 5698d 20h /
30 First version with functional verification results. fafa1971 5775d 18h /
29 Using code.txt from hello.c fafa1971 5783d 14h /
28 Changed NOR operator from (a~|b) to ~(a|b) fafa1971 5783d 19h /
27 Corrected problems with synthesis and removed system control registers fafa1971 5789d 18h /
26 Changed blocking / non-blocking assignments for MUL and DIV requests fafa1971 5789d 18h /
25 For now the top-level for synthesis is just m1_cpu fafa1971 5789d 18h /
24 Corrected include dirs fafa1971 5789d 18h /
23 New script using the correct command file for synthesis with Xilinx ISE WebPack fafa1971 5789d 18h /
22 Added script file for synthesis with Xilinx ISE WebPack fafa1971 5789d 18h /
21 First revision (you should substitute '~' char with real path). fafa1971 5796d 12h /
20 Used only lower bits also for SRAV instruction. fafa1971 5815d 00h /
19 Added changes suggested by Paolo Piscopo & Simone Lunardo to fix the bugs they found. fafa1971 5824d 19h /

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