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Rev	Log message	Author	Age	Path
21	Fix for XST synthesis error and improve readibility (by Andreas Bergmann).	mikel262	5586d 08h	/
20	Fix for XST synthesis error and improve readibility (by Andreas Bergman).	mikel262	5586d 08h	/
19	This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_6'.		6611d 04h	/
18	Minor fixes. This release is FPGA proven.	mikel262	6611d 04h	/
17	This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_5'.		6633d 01h	/
16	Documentation update, minor fixes	mikel262	6633d 01h	/
15	Redesigned. Fully pipelined, always ready for data design	mikel262	6633d 02h	/
14	This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_4'.		6637d 01h	/
13	performance improved by 8%, latency reduced to 94 cycles	mikel262	6637d 01h	/
12	This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_3'.		6638d 01h	/
11	changed ROM memory model to synchronous	mikel262	6638d 01h	/
10	+ moved memory allocation request to where it should be + reduced latency to 104 cycles	mikel262	6639d 02h	/
9	This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_2'.		6641d 13h	/
8	Updated DOC	mikel262	6641d 13h	/
7	documentation update. minor area optimization.	mikel262	6642d 00h	/
6	minor updates	mikel262	6643d 00h	/
5	This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_1'.		6643d 02h	/
4	area optimization - 100 slices less	mikel262	6643d 02h	/
3	This commit was manufactured by cvs2svn to create tag 'MDCT_B10'.		6643d 14h	/
2	Initial import (Beta Release)	mikel262	6643d 14h	/
1	Standard project directories initialized by cvs2svn.		6643d 14h	/

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