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Rev Log message Author Age Path
26 Added old uploaded documents to new repository. root 5587d 06h /
25 Added old uploaded documents to new repository. root 5587d 19h /
24 New directory structure. root 5587d 19h /
23 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_8'. 5590d 01h /
22 project released under LGPL mikel262 5590d 01h /
21 Fix for XST synthesis error and improve readibility (by Andreas Bergmann). mikel262 5590d 02h /
20 Fix for XST synthesis error and improve readibility (by Andreas Bergman). mikel262 5590d 02h /
19 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_6'. 6614d 22h /
18 Minor fixes. This release is FPGA proven. mikel262 6614d 22h /
17 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_5'. 6636d 18h /
16 Documentation update, minor fixes mikel262 6636d 18h /
15 Redesigned. Fully pipelined, always ready for data design mikel262 6636d 20h /
14 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_4'. 6640d 19h /
13 performance improved by 8%, latency reduced to 94 cycles mikel262 6640d 19h /
12 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_3'. 6641d 18h /
11 changed ROM memory model to synchronous mikel262 6641d 18h /
10 + moved memory allocation request to where it should be
+ reduced latency to 104 cycles		 mikel262 6642d 20h /
9 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_2'. 6645d 07h /
8 Updated DOC mikel262 6645d 07h /
7 documentation update. minor area optimization. mikel262 6645d 18h /
6 minor updates mikel262 6646d 18h /
5 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_1'. 6646d 19h /
4 area optimization - 100 slices less mikel262 6646d 19h /
3 This commit was manufactured by cvs2svn to create tag 'MDCT_B10'. 6647d 07h /
2 Initial import (Beta Release) mikel262 6647d 07h /
1 Standard project directories initialized by cvs2svn. 6647d 07h /

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