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Rev Log message Author Age Path
43 stall readded mikel262 5335d 13h /
42 Added backpressure/stallability of output interface. mikel262 5339d 01h /
41 Fixed RLE ZRL bug occurring at end of 8x8 block mikel262 5476d 12h /
40 Fixed few bugs in BUF_FIFO and RLE encoder. mikel262 5519d 03h /
39 bug fix. mikel262 5522d 02h /
38 Reduced processing latency of Huffman encoding mikel262 5547d 02h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5551d 06h /
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5553d 02h /
35 Added check for image width in testbench. mikel262 5553d 14h /
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5553d 22h /
33 mikel262 5554d 07h /
32 mikel262 5555d 02h /
31 Specification update, minor area improvements in BUF_FIFO. mikel262 5558d 03h /
30 mikel262 5558d 16h /
29 mikel262 5559d 00h /
28 BU_FIFO SUB_RAM is now monolithic single block used by all SubFIFO - effect much less memory block usage. mikel262 5559d 00h /
27 mikel262 5561d 12h /
26 mikel262 5561d 13h /
25 moved from branch to trunk mikel262 5561d 13h /
24 mikel262 5561d 13h /
23 mikel262 5562d 23h /
22 Changed divider to use reciprocal lookup table. Improved Huffman processing time. BUF_FIFO almost full signal modified. mikel262 5564d 00h /
21 Huffman.vhd processing latency shortened. mikel262 5564d 23h /
20 Added compressed JPEG output file from testbench mikel262 5565d 01h /
19 Timing improved in MDCT and in Huffman mikel262 5565d 02h /
18 Huffman old design restored. Simulation HOWTO added. mikel262 5565d 03h /
17 return to original version, better timing, smaller area but higher processing time mikel262 5565d 23h /
16 Huffman timing improved mikel262 5566d 00h /
15 mikel262 5566d 02h /
14 timing improve mikel262 5567d 00h /

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