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Rev Log message Author Age Path
45 stall re-added mikel262 5352d 05h /
44 stall re-added mikel262 5352d 05h /
43 stall readded mikel262 5352d 05h /
42 Added backpressure/stallability of output interface. mikel262 5355d 17h /
41 Fixed RLE ZRL bug occurring at end of 8x8 block mikel262 5493d 04h /
40 Fixed few bugs in BUF_FIFO and RLE encoder. mikel262 5535d 19h /
39 bug fix. mikel262 5538d 17h /
38 Reduced processing latency of Huffman encoding mikel262 5563d 18h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5567d 22h /
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5569d 17h /
35 Added check for image width in testbench. mikel262 5570d 06h /
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5570d 14h /
33 mikel262 5570d 23h /
32 mikel262 5571d 18h /
31 Specification update, minor area improvements in BUF_FIFO. mikel262 5574d 19h /
30 mikel262 5575d 07h /
29 mikel262 5575d 15h /
28 BU_FIFO SUB_RAM is now monolithic single block used by all SubFIFO - effect much less memory block usage. mikel262 5575d 15h /
27 mikel262 5578d 04h /
26 mikel262 5578d 04h /
25 moved from branch to trunk mikel262 5578d 04h /
24 mikel262 5578d 05h /
23 mikel262 5579d 15h /
22 Changed divider to use reciprocal lookup table. Improved Huffman processing time. BUF_FIFO almost full signal modified. mikel262 5580d 16h /
21 Huffman.vhd processing latency shortened. mikel262 5581d 15h /
20 Added compressed JPEG output file from testbench mikel262 5581d 16h /
19 Timing improved in MDCT and in Huffman mikel262 5581d 18h /
18 Huffman old design restored. Simulation HOWTO added. mikel262 5581d 18h /
17 return to original version, better timing, smaller area but higher processing time mikel262 5582d 15h /
16 Huffman timing improved mikel262 5582d 15h /

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