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Subversion Repositories mod_sim_exp

[/] - Rev 85

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Rev	Log message	Author	Age	Path
85	changed so that reset now also affects slave register	JonasDC	4147d 07h	/
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4148d 16h	/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4150d 17h	/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4167d 13h	/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4167d 13h	/
80	renamed to version 1.1 to follow the versioning system	JonasDC	4177d 07h	/
79	Tag for version 1.3 (with new ram style	JonasDC	4177d 07h	/
78	updated documentation with new RAM style information	JonasDC	4177d 07h	/
77	found fault in code, now synthesizes normally	JonasDC	4183d 04h	/
76	testbench update	JonasDC	4185d 15h	/
75	made rw_address a vector of a fixed width	JonasDC	4185d 15h	/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4188d 11h	/
73	updated plb interface, mem_style and device generics added	JonasDC	4189d 11h	/
72	deleted old resources	JonasDC	4190d 11h	/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4190d 11h	/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4190d 11h	/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4190d 11h	/
68	branch no longer needed	JonasDC	4190d 13h	/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4190d 14h	/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4190d 14h	/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4198d 06h	/
64	added synthesis reports of xilinx and altera	JonasDC	4198d 11h	/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4198d 11h	/
62	not used anymore	JonasDC	4198d 14h	/
61	updated comments, added optional altera constraint	JonasDC	4198d 14h	/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4201d 04h	/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4201d 05h	/
58	made fifo full a warning	JonasDC	4204d 05h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4204d 05h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4204d 08h	/

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[/] - Rev 85

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