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Rev Log message Author Age Path
177 Fixed comments in RTC module jshamlet 2907d 22h /
176 Fixed documentation errors,
Modified uSec_Tick such that it is always generated regardless of the interval.
jshamlet 2912d 19h /
175 Added 4 and 8-bit LCD interfaces with backlight and contrast DACs jshamlet 2913d 00h /
174 Added ROM/RAM wrappers jshamlet 3107d 19h /
173 Added a couple of useful interfaces for detecting button presses and clock changes. jshamlet 3107d 19h /
172 General code cleanup jshamlet 3107d 19h /
171 Fixed comments for offsets 0x0 - 0x3 to indicate the read value jshamlet 3107d 19h /
170 Added 24-bit resolution epoch timer / alarm clock jshamlet 3107d 19h /
169 Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. jshamlet 3162d 20h /
168 Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component,
jshamlet 3941d 16h /
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.
jshamlet 3949d 15h /
166 fixed additional issues with range checking on PCREL relocations for open8, added test cases to verify, catch tree up with binutils datestamp 20120301 khays 4513d 16h /
165 fixed issues with PC relative fixups in the linker khays 4514d 23h /
164 Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. jshamlet 4585d 10h /
163 sync with binutils 2.22.51.20111114 khays 4622d 22h /
162 Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set. jshamlet 4676d 03h /
161 synchronize binutils/ with gnu dev tree of 2.21.53.20110828 khays 4699d 22h /
160 synchronize binutils/gas with gnu dev tree of 2.21.53.20110828 khays 4699d 22h /
159 synchronize binutils/gold with gnu dev tree of 2.21.53.20110828 khays 4699d 22h /
158 synchronize binutils/opcodes with gnu dev tree of 2.21.53.20110828 khays 4699d 22h /
157 synchronize binutils/ld with gnu dev tree of 2.21.53.20110828 khays 4699d 22h /
156 Optimized for timing,
Flattened block structure to single entity.
jshamlet 4732d 18h /
155 Fixed additional interrupt logic bug,
Optimized several blocks - including ALU, stack, program counter, and data path.
jshamlet 4733d 13h /
154 Fixed problem with missing data path override in interrupt logic. Should resolve issues with processor crashing when an interrupt occurs as a STO instruction is being executed. jshamlet 4738d 16h /
153 Fixed bug in interrupt logic that caused stack pointer to increment if interrupt occurred as specific instructions were being decoded,
Fixed bug in interrupt logic where instruction caching would remain enabled during an interrupt, causing improper execution depending on what instruction was in the decode stage as the interrupt is trigered.
jshamlet 4765d 11h /
152 Correct the descriptions for GMSK and SMSK instructions in the Open8 Assembly Language Reference khays 4773d 14h /
151 Fixed STO instruction and interrupt logic to avoid address bus corruption issues. jshamlet 4775d 14h /
150 Updated the assembly language reference to add the CLR pseudo-mnemonic khays 4775d 22h /
149 added clr "Clear Accumulator" pseudo-instruction khays 4776d 00h /
148 catch up with binutils trunk through date-version 20110613 khays 4776d 18h /

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