URL https://opencores.org/ocsvn/open_hitter/open_hitter/trunk

Subversion Repositories open_hitter

[/] - Rev 22

Rev	Log message	Author	Age	Path
22	mixed rising_edge / falling_edge logic removed	stvhawes	3278d 22h	/
21	flakey sim bugs (1/10 test 2 fails)	stvhawes	3279d 00h	/
20	search_control_sim prepped	stvhawes	3285d 19h	/
19	search_control is up for simulation (ghdl) - tidied extra testbenches	stvhawes	3292d 19h	/
18	search_control is up for simulation (ghdl)	stvhawes	3292d 19h	/
17	persistent bug: search_control_wrapper.vhd:230:21:@36us:(assertion error): search_control_wrapper: test: 3 bad id	stvhawes	3298d 05h	/
16	minor fixes to search_control test bench	stvhawes	3304d 16h	/
15	adding in search_control and testbench	stvhawes	3305d 20h	/
14	search_item_wrapper bench debugged	stvhawes	3311d 17h	/
13	test bench for search_item	stvhawes	3314d 21h	/
12	wrapper test for search_item	stvhawes	3320d 07h	/
11	multiplex searh item added	stvhawes	3320d 23h	/
10	split source files to sime and rtl	stvhawes	3334d 22h	/
9	highlevel block diagram added	stvhawes	3335d 19h	/
8	sim sequence error fixed, so 20% success -> 100% success for unit test on fpga	stvhawes	3335d 21h	/
7	split clock/byte_ready and fix logic	stvhawes	3340d 15h	/
6	fixing synthesizable	stvhawes	3341d 23h	/
5	fixing synthesizable	stvhawes	3342d 04h	/
4	developing ideas around unit test / fpga verification	stvhawes	3342d 16h	/
3	developing ideas around unit test / fpga verification	stvhawes	3342d 16h	/
2	initial sources, wrappers for regression test harness	stvhawes	3353d 18h	/
1	The project and the structure was created	root	3355d 13h	/