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50 Adding function to do combinational unsigned division, problem that it would change the clock to 5Mhz :(
The combinational delay increased a lot

udivResult := CONV_STD_LOGIC_VECTOR(udivision(unsigned(A),unsigned(B)), 32);
intermediate_S := udivResult(nBits downto 0);
leonardoaraujo.santos 4428d 19h /
49 Adding docs (Unsigned Division) leonardoaraujo.santos 4428d 19h /
48 Working on jump instrunctions (Imediate) leonardoaraujo.santos 4429d 20h /
47 Changing the Multiplexer3_1 (The one who chooses the alu input) selection signals leonardoaraujo.santos 4430d 04h /
46 Working on load instructions leonardoaraujo.santos 4430d 05h /
45 Preparing to test the load operation leonardoaraujo.santos 4430d 20h /
44 Start to work on store operation leonardoaraujo.santos 4430d 21h /
43 Solved an issue where the imediate values where switched from the memory values leonardoaraujo.santos 4431d 02h /
42 Changing Multiplexer to use the constants
Changing timing on top testbench (To have valid and stable data when the memory enable is asserted)
leonardoaraujo.santos 4431d 03h /
41 Adding interesting website with VHDL I/O tutorial leonardoaraujo.santos 4431d 14h /
40 Adding feature to create file with source code tested from testControlUnit.vhd leonardoaraujo.santos 4431d 14h /
39 Adding file i/o support (Still on test) leonardoaraujo.santos 4431d 21h /
38 Working a little bit on documentation leonardoaraujo.santos 4432d 14h /
37 Working a little bit on documentation leonardoaraujo.santos 4432d 14h /
36 Adding top level testbench leonardoaraujo.santos 4432d 14h /
35 Adding test to add values from imediate... Now I will work a little bit on the tests with the ControlUnit and DataPath together leonardoaraujo.santos 4433d 03h /
34 Fixing time issues on ControlUnit and adding more tests leonardoaraujo.santos 4433d 15h /
33 Continue testControlUnit and fixing some errors on ControlUnit leonardoaraujo.santos 4433d 18h /
32 Cleaning room to start to play with the control unit testbench leonardoaraujo.santos 4434d 01h /
31 Adding store and load instructions ... (Now is a good time to stop a little bit and work on the testbench of the CPU) leonardoaraujo.santos 4438d 21h /
30 Adding top level CPU file, fixing some problems on ControlUnit.vhd leonardoaraujo.santos 4439d 01h /
29 Udating DataPath.vhd with the flags comming out from Alu, added jump instructions into the ControlUnit.vhd leonardoaraujo.santos 4439d 17h /
28 Adding flags and shift/rotate operations to the Alu.vhd leonardoaraujo.santos 4439d 18h /
27 Changing Datapath for operations with Imediate values, working on the Control Unit... (Datapath testbench was updated also) leonardoaraujo.santos 4441d 19h /
26 leonardoaraujo.santos 4442d 20h /
25 Working on ControlUnit leonardoaraujo.santos 4443d 19h /
24 Working on the Control unit, (Don't forget to add the Carry, Flags Out, shift/rotates on the Alu...) leonardoaraujo.santos 4444d 18h /
23 Updating bibliography leonardoaraujo.santos 4446d 15h /
22 Adding ControlUnit skeleton leonardoaraujo.santos 4446d 15h /
21 Add new test case on DataPath leonardoaraujo.santos 4446d 15h /

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