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Subversion Repositories openmsp430

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Rev	Log message	Author	Age	Path
112	Modified comment.	olivier.girard	4799d 08h	/
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4800d 08h	/
110	Rework of the GUI for the software development tools. Added possibility to give custom information through the omsp_alias.xml file.	olivier.girard	4801d 08h	/
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4854d 17h	/
108	Add serial debug interface tasks to the Actel fpga simulation environment.	olivier.girard	4856d 06h	/
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4856d 06h	/
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4856d 07h	/
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4871d 07h	/
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4875d 09h	/
103	Removed the timescale from all RTL files. Added possibility to exclude the "includes" statements from the RTL.	olivier.girard	4876d 14h	/
102	Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ). The following PUSH instructions are now working as expected: - indexed mode: PUSH x(R1) - indirect register mode: PUSH @R1 - indirect autoincrement: PUSH @R1+	olivier.girard	4877d 07h	/
101	Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source.	olivier.girard	4877d 08h	/
100	Update HTML documentation with Actel's FPGA implementation example (file & directory description section).	olivier.girard	4880d 07h	/
99	Small fix for CVER simulator support.	olivier.girard	4881d 08h	/
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4881d 08h	/
97	Update Tools' Windows executables with EraseROM command fix.	olivier.girard	4882d 08h	/
96	Fixed EraseROM command in the TCL library of the Software development tools.	olivier.girard	4882d 08h	/
95	Update some test patterns for the additional simulator supports.	olivier.girard	4885d 08h	/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4885d 08h	/
93	Update Tools' Windows executables.	olivier.girard	4889d 08h	/
92	Fixed bug where the openmsp430-minidebug application shows data memory size instead of program memory size and program memory size instead of data memory size. Thanks to "dir" for reporting the bug :-)	olivier.girard	4889d 09h	/
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4889d 09h	/
90	Update windows executables for the tools.	olivier.girard	4904d 15h	/
89	Update the loader tool to support Intel-HEX format.	olivier.girard	4904d 15h	/
88	Update windows executables for the tools.	olivier.girard	4904d 15h	/
87	Minor update of gdbproxy to allow sourcing some custom tcl scripts. Major update of the minidebugger (complete re-work of the GUI).	olivier.girard	4904d 15h	/
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4912d 06h	/
85	Diverse RTL cosmetic updates.	olivier.girard	4912d 08h	/
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	4917d 09h	/
83	Add Oscilloscope screenshot + link to the original game.	olivier.girard	4963d 09h	/

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