OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] - Rev 49

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
49 Temporar documentation removal because of broken SVN update. olivier.girard 5305d 09h /
48 Re-add html documentation. olivier.girard 5305d 09h /
47 Temporar documentation removal because of broken SVN update. olivier.girard 5305d 09h /
46 Re-add html documentation. olivier.girard 5305d 10h /
45 Temporar documentation removal because of broken SVN update. olivier.girard 5305d 10h /
44 Update documentation with the "Integration and Connectivity" section. olivier.girard 5305d 10h /
43 Re-add documentation (earlier pdf was broken). olivier.girard 5329d 09h /
42 olivier.girard 5329d 09h /
41 Update bitstream & SVN ignore patterns. olivier.girard 5329d 09h /
40 Minor updates. olivier.girard 5329d 10h /
39 Update FPGA projects with new openMSP430 core. olivier.girard 5329d 10h /
38 Remove old core version. olivier.girard 5329d 11h /
37 olivier.girard 5329d 11h /
36 Remove old core version. olivier.girard 5329d 11h /
35 Update documentation to reflect the latest Verilog changes. olivier.girard 5329d 11h /
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5329d 12h /
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5329d 13h /
32 Minor update to the HTML documentation + add some SVN ignore properties to the Altera FPGA project simulation directory. olivier.girard 5331d 10h /
31 Update documentation (new Altera FPGA project + diverse minor updates) olivier.girard 5331d 10h /
30 Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution). olivier.girard 5331d 11h /
29 Add Altera Cyclone II FPGA project example. olivier.girard 5331d 11h /
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5339d 19h /
27 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5339d 19h /
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5339d 19h /
25 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5429d 17h /
24 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5429d 17h /
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5450d 15h /
22 Updated some links in the HTML documentation. olivier.girard 5463d 12h /
21 added discussion group info olivier.girard 5475d 13h /
20 added some SVN ignore patterns.
small update to html documentation		 olivier.girard 5476d 09h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.