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Rev Log message Author Age Path
72 Toolchain install script: or1ksim location changed, few tweaks julius 5217d 02h /
71 ORPSoC board builds, adding readmes julius 5233d 09h /
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5237d 13h /
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5237d 14h /
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5240d 06h /
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5240d 09h /
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5260d 07h /
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5264d 13h /
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5267d 08h /
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5277d 05h /
62 This material is part of the separate website downloads directory. jeremybennett 5288d 08h /
61 The build directory should not be part of the SVN configuration. jeremybennett 5288d 09h /
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5295d 02h /
59 Toolchain install script gcc patch change and gdb configure change julius 5316d 02h /
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5319d 01h /
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5324d 05h /
56 adding generic pll model to orpsoc julius 5332d 07h /
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5334d 21h /
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5345d 04h /
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5363d 05h /
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5364d 01h /
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5378d 03h /
50 Adding or32_funcs.S julius 5378d 07h /
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5396d 21h /
48 Adds an initialization to keep GCC happy in jp1_ll_read_jp1. jeremybennett 5397d 00h /
47 debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions julius 5406d 08h /
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5412d 09h /
45 Orpsoc eth test fix and script error message update julius 5419d 08h /
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5448d 08h /
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 5472d 05h /

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