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Rev Log message Author Age Path
84 Remove duplicated directories. jeremybennett 5222d 01h /
83 Fix to use -1 to invalidate cache tags. Suggested by John Alfredo. jeremybennett 5222d 15h /
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.
jeremybennett 5222d 16h /
81 Directory no longer used. jeremybennett 5222d 16h /
80 Add missing configuration files to SVN. jeremybennett 5222d 19h /
79 Fixed retry loop in or_debug_proxy, hopefully more stable when physically resetting the board julius 5234d 20h /
78 Fixed typo in Silos workaround script rherveille 5235d 15h /
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour
rherveille 5235d 16h /
76 Added: +libext+.v
Added: +incdir+.
rherveille 5236d 15h /
75 Fixed toolchain script's cygwin ncurses check julius 5241d 18h /
74 Toolchain script fix for ncurses header checking julius 5259d 20h /
73 toolchain script error fix julius 5259d 21h /
72 Toolchain install script: or1ksim location changed, few tweaks julius 5262d 18h /
71 ORPSoC board builds, adding readmes julius 5279d 01h /
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5283d 06h /
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5283d 07h /
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5285d 22h /
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5286d 01h /
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5305d 23h /
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5310d 05h /
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5313d 00h /
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5322d 21h /
62 This material is part of the separate website downloads directory. jeremybennett 5334d 01h /
61 The build directory should not be part of the SVN configuration. jeremybennett 5334d 01h /
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5340d 18h /
59 Toolchain install script gcc patch change and gdb configure change julius 5361d 19h /
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5364d 17h /
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5369d 21h /
56 adding generic pll model to orpsoc julius 5377d 23h /
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5380d 14h /

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