| Rev |
Log message |
Author |
Age |
Path |
| 90 |
Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). |
jeremybennett |
5195d 06h |
/ |
| 89 |
Tidy up for latest bug fixes. |
jeremybennett |
5195d 13h |
/ |
| 88 |
Fix to bug 1710. |
jeremybennett |
5195d 13h |
/ |
| 87 |
Typo fixed. |
jeremybennett |
5195d 13h |
/ |
| 86 |
Bug 1723 fixed (PS2 keyboard error message clarification). |
jeremybennett |
5195d 13h |
/ |
| 85 |
Bug 1773 (RSP usage with ELF image preloaded) fixed. |
jeremybennett |
5195d 14h |
/ |
| 84 |
Remove duplicated directories. |
jeremybennett |
5195d 14h |
/ |
| 83 |
Fix to use -1 to invalidate cache tags. Suggested by John Alfredo. |
jeremybennett |
5196d 04h |
/ |
| 82 |
Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".
Incorporate Mark Jarvis's fixes for Mac OS X. |
jeremybennett |
5196d 05h |
/ |
| 81 |
Directory no longer used. |
jeremybennett |
5196d 05h |
/ |
| 80 |
Add missing configuration files to SVN. |
jeremybennett |
5196d 09h |
/ |
| 79 |
Fixed retry loop in or_debug_proxy, hopefully more stable when physically resetting the board |
julius |
5208d 10h |
/ |
| 78 |
Fixed typo in Silos workaround script |
rherveille |
5209d 05h |
/ |
| 77 |
Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour |
rherveille |
5209d 05h |
/ |
| 76 |
Added: +libext+.v
Added: +incdir+. |
rherveille |
5210d 05h |
/ |
| 75 |
Fixed toolchain script's cygwin ncurses check |
julius |
5215d 07h |
/ |
| 74 |
Toolchain script fix for ncurses header checking |
julius |
5233d 10h |
/ |
| 73 |
toolchain script error fix |
julius |
5233d 11h |
/ |
| 72 |
Toolchain install script: or1ksim location changed, few tweaks |
julius |
5236d 08h |
/ |
| 71 |
ORPSoC board builds, adding readmes |
julius |
5252d 14h |
/ |
| 70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5256d 19h |
/ |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5256d 20h |
/ |
| 68 |
Fixed up a couple of Makefile things in ORPSoCv2 |
julius |
5259d 12h |
/ |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5259d 14h |
/ |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5279d 13h |
/ |
| 65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5283d 19h |
/ |
| 64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5286d 14h |
/ |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5296d 11h |
/ |
| 62 |
This material is part of the separate website downloads directory. |
jeremybennett |
5307d 14h |
/ |
| 61 |
The build directory should not be part of the SVN configuration. |
jeremybennett |
5307d 14h |
/ |
