| Rev |
Log message |
Author |
Age |
Path |
| 91 |
Tidy up of some obsolete configuration code. |
jeremybennett |
5225d 08h |
/ |
| 90 |
Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). |
jeremybennett |
5225d 09h |
/ |
| 89 |
Tidy up for latest bug fixes. |
jeremybennett |
5225d 15h |
/ |
| 88 |
Fix to bug 1710. |
jeremybennett |
5225d 16h |
/ |
| 87 |
Typo fixed. |
jeremybennett |
5225d 16h |
/ |
| 86 |
Bug 1723 fixed (PS2 keyboard error message clarification). |
jeremybennett |
5225d 16h |
/ |
| 85 |
Bug 1773 (RSP usage with ELF image preloaded) fixed. |
jeremybennett |
5225d 17h |
/ |
| 84 |
Remove duplicated directories. |
jeremybennett |
5225d 17h |
/ |
| 83 |
Fix to use -1 to invalidate cache tags. Suggested by John Alfredo. |
jeremybennett |
5226d 07h |
/ |
| 82 |
Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".
Incorporate Mark Jarvis's fixes for Mac OS X. |
jeremybennett |
5226d 08h |
/ |
| 81 |
Directory no longer used. |
jeremybennett |
5226d 08h |
/ |
| 80 |
Add missing configuration files to SVN. |
jeremybennett |
5226d 11h |
/ |
| 79 |
Fixed retry loop in or_debug_proxy, hopefully more stable when physically resetting the board |
julius |
5238d 12h |
/ |
| 78 |
Fixed typo in Silos workaround script |
rherveille |
5239d 08h |
/ |
| 77 |
Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour |
rherveille |
5239d 08h |
/ |
| 76 |
Added: +libext+.v
Added: +incdir+. |
rherveille |
5240d 07h |
/ |
| 75 |
Fixed toolchain script's cygwin ncurses check |
julius |
5245d 10h |
/ |
| 74 |
Toolchain script fix for ncurses header checking |
julius |
5263d 13h |
/ |
| 73 |
toolchain script error fix |
julius |
5263d 14h |
/ |
| 72 |
Toolchain install script: or1ksim location changed, few tweaks |
julius |
5266d 11h |
/ |
| 71 |
ORPSoC board builds, adding readmes |
julius |
5282d 17h |
/ |
| 70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5286d 22h |
/ |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5286d 23h |
/ |
| 68 |
Fixed up a couple of Makefile things in ORPSoCv2 |
julius |
5289d 14h |
/ |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5289d 17h |
/ |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5309d 15h |
/ |
| 65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5313d 21h |
/ |
| 64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5316d 17h |
/ |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5326d 14h |
/ |
| 62 |
This material is part of the separate website downloads directory. |
jeremybennett |
5337d 17h |
/ |
