OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] - Rev 452

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 5016d 05h /
451 More tidying up. jeremybennett 5020d 01h /
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 5020d 05h /
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 5022d 01h /
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 5022d 11h /
447 Updates to register order. jeremybennett 5023d 05h /
446 gdb-7.2 gdbserver updates. julius 5024d 00h /
445 gdbserver update to use kernel port ptrace register definitions. julius 5024d 20h /
444 Changes to ABI handling of varargs. jeremybennett 5025d 05h /
443 Work in progress on more efficient Ethernet. jeremybennett 5025d 09h /
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 5025d 23h /
441 Changes for gdbserver. jeremybennett 5026d 06h /
440 Updated documentation to describe new Ethernet usage. jeremybennett 5027d 01h /
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 5029d 05h /
438 Fix to newlib header and library locations. jeremybennett 5032d 05h /
437 Or1ksim - ethernet peripheral update, working much better. julius 5034d 19h /
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 5035d 19h /
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.
julius 5035d 20h /
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 5039d 01h /
433 New single program interrupt test programs. jeremybennett 5040d 04h /
432 Updates to handle interrupts correctly. jeremybennett 5040d 05h /
431 Updated and move OR1200 supplementary manual.

or_debug_proxy GDB RSP interface fix.

ORPSoC S/W and makefile updates.
julius 5042d 04h /
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 5043d 01h /
429 or1ksim update - remove debug printfs from eth MDIO emulation function
and fix illegal instruction vector jump for invalid instructions.
julius 5043d 05h /
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 5046d 01h /
427 Fixes for C++ to correspond to fixes in uClibc. jeremybennett 5047d 09h /
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...
julius 5048d 19h /
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.
julius 5048d 20h /
424 C++ library, needed for C++ compiler. jeremybennett 5049d 07h /
423 Minor typo fixed. jeremybennett 5049d 10h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.