OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] - Rev 459

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
459 Add option to bld-all.sh to explicitly set control load of make, and fix typos. julius 4945d 16h /
458 or1ksim testsuite updates julius 4946d 14h /
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4955d 04h /
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4955d 05h /
455 Updated to support threads. Does require thread debugging enabled in uClibc. jeremybennett 4959d 07h /
454 Updated to incorporate pthreads for Linux tool chain. jeremybennett 4961d 09h /
453 Updates to support constructor/destructor initialization for uClibc. jeremybennett 4961d 20h /
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 4962d 04h /
451 More tidying up. jeremybennett 4966d 00h /
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 4966d 04h /
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 4968d 00h /
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 4968d 11h /
447 Updates to register order. jeremybennett 4969d 04h /
446 gdb-7.2 gdbserver updates. julius 4969d 23h /
445 gdbserver update to use kernel port ptrace register definitions. julius 4970d 20h /
444 Changes to ABI handling of varargs. jeremybennett 4971d 04h /
443 Work in progress on more efficient Ethernet. jeremybennett 4971d 08h /
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4971d 22h /
441 Changes for gdbserver. jeremybennett 4972d 05h /
440 Updated documentation to describe new Ethernet usage. jeremybennett 4973d 00h /
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4975d 04h /
438 Fix to newlib header and library locations. jeremybennett 4978d 04h /
437 Or1ksim - ethernet peripheral update, working much better. julius 4980d 18h /
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 4981d 19h /
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4981d 19h /
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 4985d 01h /
433 New single program interrupt test programs. jeremybennett 4986d 03h /
432 Updates to handle interrupts correctly. jeremybennett 4986d 04h /
431 Updated and move OR1200 supplementary manual.

or_debug_proxy GDB RSP interface fix.

ORPSoC S/W and makefile updates.		 julius 4988d 03h /
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 4989d 01h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.