OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] - Rev 467

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
467 ORPmon - bug fixes and clean up. julius 4918d 00h /
466 ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README		 julius 4918d 05h /
465 ORPSoC SPI flash load Makefile and README updates. julius 4918d 20h /
464 More ORPmon updates. julius 4918d 20h /
463 ORPmon update julius 4918d 23h /
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.		 julius 4919d 04h /
461 Updated to be much stricter about usage. jeremybennett 4921d 00h /
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 4921d 01h /
459 Add option to bld-all.sh to explicitly set control load of make, and fix typos. julius 4921d 07h /
458 or1ksim testsuite updates julius 4922d 05h /
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4930d 20h /
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4930d 21h /
455 Updated to support threads. Does require thread debugging enabled in uClibc. jeremybennett 4934d 23h /
454 Updated to incorporate pthreads for Linux tool chain. jeremybennett 4937d 01h /
453 Updates to support constructor/destructor initialization for uClibc. jeremybennett 4937d 12h /
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 4937d 20h /
451 More tidying up. jeremybennett 4941d 16h /
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 4941d 20h /
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 4943d 16h /
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 4944d 02h /
447 Updates to register order. jeremybennett 4944d 20h /
446 gdb-7.2 gdbserver updates. julius 4945d 15h /
445 gdbserver update to use kernel port ptrace register definitions. julius 4946d 11h /
444 Changes to ABI handling of varargs. jeremybennett 4946d 20h /
443 Work in progress on more efficient Ethernet. jeremybennett 4947d 00h /
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4947d 14h /
441 Changes for gdbserver. jeremybennett 4947d 21h /
440 Updated documentation to describe new Ethernet usage. jeremybennett 4948d 16h /
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4950d 20h /
438 Fix to newlib header and library locations. jeremybennett 4953d 20h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.