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Rev Log message Author Age Path
982 Moved to sim/bin lampret 7959d 03h /
981 First checkin. lampret 7959d 03h /
980 Removed sim.tcl that shouldn't be here. lampret 7959d 03h /
979 Removed old test case binaries. lampret 7959d 03h /
978 Added variable delay for SRAM. lampret 7959d 03h /
977 Added store buffer. lampret 7959d 03h /
976 Added store buffer lampret 7959d 03h /
975 First checkin lampret 7959d 03h /
974 Enabled what works on or1ksim and disabled other tests. lampret 7959d 05h /
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 7961d 09h /
972 Interrupt suorces fixed. simons 7961d 09h /
971 Now even keyboard test passes. simons 7961d 12h /
970 Testbench is now running on ORP architecture platform. simons 7962d 01h /
969 Checking in except directory. lampret 7962d 16h /
968 Checking in utils directory. lampret 7962d 16h /
967 Checking in mul directory. lampret 7962d 16h /
966 Checking in cbasic directory. lampret 7962d 16h /
965 Checking in basic directory. lampret 7962d 16h /
964 Checking in support directory. lampret 7962d 16h /
963 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7962d 16h /
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 7962d 16h /
961 uart16550 RTL files renamed/added/removed. lampret 7962d 17h /
960 Directory cleanup. lampret 7962d 17h /
959 Fixed size of generic flash/sram to exactly 2MB lampret 7963d 16h /
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 7963d 16h /
957 Flash at 0x04000000 RAM at 0x00000000. Only MMU test works. simons 7964d 02h /
956 Changed to work with or32-uclinux tool chain. Everything works except keyboard test. simons 7964d 06h /
955 typos and grammar fixed markom 7965d 08h /
954 some debugging code cleanup markom 7965d 11h /
953 burst detection for bytes & halfwords added markom 7965d 12h /

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