URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] - Rev 988

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Rev	Log message	Author	Age	Path
988	ORP architecture supported.	simons	7966d 17h	/
987	ORP architecture supported.	simons	7967d 00h	/
986	outputs out of function are not registered anymore	markom	7967d 01h	/
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	7967d 13h	/
984	Disable SB until it is tested	lampret	7967d 13h	/
983	First checkin	lampret	7967d 15h	/
982	Moved to sim/bin	lampret	7967d 15h	/
981	First checkin.	lampret	7967d 15h	/
980	Removed sim.tcl that shouldn't be here.	lampret	7967d 15h	/
979	Removed old test case binaries.	lampret	7967d 15h	/
978	Added variable delay for SRAM.	lampret	7967d 15h	/
977	Added store buffer.	lampret	7967d 15h	/
976	Added store buffer	lampret	7967d 15h	/
975	First checkin	lampret	7967d 15h	/
974	Enabled what works on or1ksim and disabled other tests.	lampret	7967d 17h	/
973	generated cuc top scheduler builds without syntax errors; not tested yet	markom	7969d 21h	/
972	Interrupt suorces fixed.	simons	7969d 21h	/
971	Now even keyboard test passes.	simons	7970d 00h	/
970	Testbench is now running on ORP architecture platform.	simons	7970d 13h	/
969	Checking in except directory.	lampret	7971d 04h	/
968	Checking in utils directory.	lampret	7971d 05h	/
967	Checking in mul directory.	lampret	7971d 05h	/
966	Checking in cbasic directory.	lampret	7971d 05h	/
965	Checking in basic directory.	lampret	7971d 05h	/
964	Checking in support directory.	lampret	7971d 05h	/
963	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7971d 05h	/
962	Fixed Xilinx trace buffer address. REported by Taylor Su.	lampret	7971d 05h	/
961	uart16550 RTL files renamed/added/removed.	lampret	7971d 05h	/
960	Directory cleanup.	lampret	7971d 05h	/
959	Fixed size of generic flash/sram to exactly 2MB	lampret	7972d 04h	/

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[/] - Rev 988

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