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Rev Log message Author Age Path
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7964d 13h /
993 Fixed IMMU bug. lampret 7964d 13h /
992 A bug when cache enabled and bus error comes fixed. simons 7964d 22h /
991 Different memory controller. simons 7964d 22h /
990 Test is now complete. simons 7964d 22h /
989 c++ is making problems so, for now, it is excluded. simons 7966d 06h /
988 ORP architecture supported. simons 7966d 22h /
987 ORP architecture supported. simons 7967d 05h /
986 outputs out of function are not registered anymore markom 7967d 06h /
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 7967d 17h /
984 Disable SB until it is tested lampret 7967d 18h /
983 First checkin lampret 7967d 19h /
982 Moved to sim/bin lampret 7967d 19h /
981 First checkin. lampret 7967d 20h /
980 Removed sim.tcl that shouldn't be here. lampret 7967d 20h /
979 Removed old test case binaries. lampret 7967d 20h /
978 Added variable delay for SRAM. lampret 7967d 20h /
977 Added store buffer. lampret 7967d 20h /
976 Added store buffer lampret 7967d 20h /
975 First checkin lampret 7967d 20h /
974 Enabled what works on or1ksim and disabled other tests. lampret 7967d 22h /
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 7970d 02h /
972 Interrupt suorces fixed. simons 7970d 02h /
971 Now even keyboard test passes. simons 7970d 05h /
970 Testbench is now running on ORP architecture platform. simons 7970d 18h /
969 Checking in except directory. lampret 7971d 09h /
968 Checking in utils directory. lampret 7971d 09h /
967 Checking in mul directory. lampret 7971d 09h /
966 Checking in cbasic directory. lampret 7971d 09h /
965 Checking in basic directory. lampret 7971d 09h /

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