URL https://opencores.org/ocsvn/pairing/pairing/trunk

Subversion Repositories pairing

[/] - Rev 26

Rev	Log message	Author	Age	Path
26	Detailed description for the ModelSim macro file and the main test bench file	homer.xing	4518d 05h	/
25	simulation scripts and readme-file explaining how to start the simulation	homer.xing	4518d 06h	/
24	LGPL claim in each source hdl file	homer.xing	4526d 06h	/
23	LGPL license text	homer.xing	4526d 06h	/
22	Change TAB to space	homer.xing	4526d 07h	/
21	Add detailed input data capture condition in the document	homer.xing	4526d 08h	/
20	Add a module and a testbench for Xilinx ISE post-route simulation	homer.xing	4527d 10h	/
19	Update synthesis result	homer.xing	4528d 03h	/
18	add synthesis result	homer.xing	4528d 03h	/
17	use logic for $f3m_mux6$	homer.xing	4528d 05h	/
16	Add synthesis configuration files	homer.xing	4528d 08h	/
15	add document. ha ha ha	homer.xing	4528d 09h	/
14	Move constraint file	homer.xing	4528d 10h	/
13	Add document and synthesis directories	homer.xing	4528d 10h	/
12	Simplify the interface of the core.	homer.xing	4528d 11h	/
11	Cheers! as fast as a rocket	homer.xing	4529d 06h	/
10	Ho ho, better circuit	homer.xing	4530d 00h	/
9	Add constrains file for ISE	homer.xing	4531d 04h	/
8	Finished Tate Pairing. Ha ha ha	homer.xing	4531d 05h	/
7	Finish inversion @ f33m	homer.xing	4539d 10h	/
6	add testbench for $f33m$.	homer.xing	4540d 09h	/
5	rename director : verilog/ -> rtl/	homer.xing	4540d 09h	/
4	add testbench	homer.xing	4541d 07h	/
3	finish Duursma Lee algorithm. doing f33m module	homer.xing	4541d 07h	/
2	upload code for Duursma-Lee algorithm. I am still developing them.	homer.xing	4542d 07h	/
1	The project and the structure was created	root	4542d 07h	/