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Rev Log message Author Age Path
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7975d 03h /
58 Removed all logic from asynchronous reset network mihad 7980d 03h /
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7980d 09h /
56 Number of state bits define was removed mihad 7981d 00h /
55 Changed state machine encoding to true one-hot mihad 7981d 00h /
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8014d 02h /
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8014d 06h /
52 Oops, never before noticed that OC header is missing mihad 8014d 10h /
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8014d 10h /
50 Got rid of undef directives mihad 8017d 02h /
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8017d 02h /
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8017d 02h /
47 Known issues repaired mihad 8017d 08h /
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8022d 02h /
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8023d 08h /
44 Added for testing of Configuration Cycles Type 1 mihad 8023d 08h /
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 8023d 08h /
42 Removed out of date files mihad 8035d 09h /
41 This commit was manufactured by cvs2svn to create tag 'rel_00'. 8114d 00h /
40 From these Wrod files PDF were created - added future improvements tadej 8114d 00h /
39 File not needed tadej 8114d 00h /
38 This file is not needed tadej 8114d 03h /
37 These files are not needed any more tadej 8114d 03h /
36 *** empty log message *** tadej 8114d 04h /
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8168d 11h /
34 Added missing include statements mihad 8183d 10h /
33 Added some testcases, removed un-needed fifo signals mihad 8184d 07h /
32 Added include statement that was missing and causing errors mihad 8192d 04h /
31 User defined constants used for Test Application tadej 8194d 23h /
30 Example of PCI testbench log file mihad 8195d 07h /

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