OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] - Rev 59

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7951d 16h /
58 Removed all logic from asynchronous reset network mihad 7956d 16h /
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7956d 22h /
56 Number of state bits define was removed mihad 7957d 13h /
55 Changed state machine encoding to true one-hot mihad 7957d 13h /
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7990d 15h /
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7990d 18h /
52 Oops, never before noticed that OC header is missing mihad 7990d 22h /
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7990d 23h /
50 Got rid of undef directives mihad 7993d 15h /
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7993d 15h /
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7993d 15h /
47 Known issues repaired mihad 7993d 21h /
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7998d 15h /
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7999d 21h /
44 Added for testing of Configuration Cycles Type 1 mihad 7999d 21h /
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7999d 21h /
42 Removed out of date files mihad 8011d 22h /
41 This commit was manufactured by cvs2svn to create tag 'rel_00'. 8090d 12h /
40 From these Wrod files PDF were created - added future improvements tadej 8090d 12h /
39 File not needed tadej 8090d 13h /
38 This file is not needed tadej 8090d 16h /
37 These files are not needed any more tadej 8090d 16h /
36 *** empty log message *** tadej 8090d 17h /
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8145d 00h /
34 Added missing include statements mihad 8159d 23h /
33 Added some testcases, removed un-needed fifo signals mihad 8160d 20h /
32 Added include statement that was missing and causing errors mihad 8168d 16h /
31 User defined constants used for Test Application tadej 8171d 12h /
30 Example of PCI testbench log file mihad 8171d 20h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.