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Rev	Log message	Author	Age	Path
73	Bug fixes, testcases added.	mihad	7826d 16h	/
72	* empty log message *	mihad	7873d 20h	/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7881d 12h	/
70	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7918d 19h	/
69	Changed BIST signal names etc..	mihad	7918d 19h	/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7922d 05h	/
67	Changed BIST signals for RAMs.	tadejm	7922d 10h	/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7925d 20h	/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7928d 18h	/
64	The testcase I just added in previous revision repaired	mihad	7928d 21h	/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7928d 22h	/
62	Added BIST signals for RAMs.	mihad	7931d 15h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7939d 15h	/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7939d 15h	/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7939d 17h	/
58	Removed all logic from asynchronous reset network	mihad	7944d 17h	/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7944d 23h	/
56	Number of state bits define was removed	mihad	7945d 13h	/
55	Changed state machine encoding to true one-hot	mihad	7945d 14h	/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7978d 16h	/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7978d 19h	/
52	Oops, never before noticed that OC header is missing	mihad	7978d 23h	/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7978d 23h	/
50	Got rid of undef directives	mihad	7981d 16h	/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7981d 16h	/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7981d 16h	/
47	Known issues repaired	mihad	7981d 22h	/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	7986d 16h	/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7987d 21h	/
44	Added for testing of Configuration Cycles Type 1	mihad	7987d 22h	/

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