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[/] - Rev 83

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Rev	Log message	Author	Age	Path
83	Cleaned up the code. No functional changes.	mihad	7853d 12h	/
82	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7867d 08h	/
81	Updated synchronization in top level fifo modules.	mihad	7867d 08h	/
80	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7870d 13h	/
79	Updated.	mihad	7870d 13h	/
78	Old files with wrong names removed.	mihad	7870d 13h	/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7870d 13h	/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7873d 13h	/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7876d 14h	/
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7876d 14h	/
73	Bug fixes, testcases added.	mihad	7876d 14h	/
72	* empty log message *	mihad	7923d 18h	/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7931d 10h	/
70	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7968d 17h	/
69	Changed BIST signal names etc..	mihad	7968d 17h	/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7972d 03h	/
67	Changed BIST signals for RAMs.	tadejm	7972d 07h	/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7975d 18h	/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7978d 16h	/
64	The testcase I just added in previous revision repaired	mihad	7978d 18h	/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7978d 20h	/
62	Added BIST signals for RAMs.	mihad	7981d 13h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7989d 13h	/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7989d 13h	/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7989d 14h	/
58	Removed all logic from asynchronous reset network	mihad	7994d 14h	/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7994d 20h	/
56	Number of state bits define was removed	mihad	7995d 11h	/
55	Changed state machine encoding to true one-hot	mihad	7995d 12h	/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	8028d 13h	/

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[/] - Rev 83

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